For several decades, semiconductor memory technologies have been successfully scaled down to achieve higher speed and higher density memory devices with lower bit cost. As the DRAM cell size is reduced, the parameters of cell operation are more crucial than ever. Due to the aggressive scaling cell, we FDQ¶WDYRLGYHUORZ&V7KLVUHVXOWVLQSRRUGDWDUHWHQWLRQWLPH and an insufficient sensing margin. Furthermore, as the cell transistor is scaled down, huge leakage current is inevitable in the case of the buried gate (BG) structure due to the weak gate controllability and interference between neighbor transistors. Contrary to the continuous scaling down trend of DRAM, NAND flash memory has made great progress towards the new era. Instead of a conventional 2D floating gate (FG) cell, 3D charge trap NAND was unveiled and successfully commercialized. By demonstrating the possibility of higher performance and robust reliability, this new NAND product is expected to provide distinguished value to customers and to expand the high-end market size. In spite of high expectation, there are still concerns about successful mass production. In this paper, the technology scaling issues of DRAM and 3D NAND flash will be reviewed and some meaningful solutions to overcome these challenges will be addressed as well as future technology prospects.