Hi Kevin and Stella,Please find the process window outliers identified by ADM team out of the first YP lot below and help to quarantine the SN attached.They are suspected as trapezoid shaped PCB and could cause high yield loss.We are discussing to arrange a small lot of DOE to input them together to record failure rate to understand the correlation of trapezoid shape to bus0/bus1 failures.Instructions below:1. Input IQC on all samples upon arrival (ETD 1/4 from YP)2. Finish stencil binning based on IQC data and correlate study with YP OQC data3. Hold the SN attached below and input only ok samples for main build4. Collect 20x to 30x samples (depending on stencil binning) and input as DOE lot to understand yield fluctuation in main build for failure mode study.5. Establish process window after DPOC based on DOE data collection