1. Please refer Christophe's mail in other file.
-- Refer Ampleon RDL design.7z for each layer of target PI1/RDL/PI2, apply same concept as feasibility to apply taped angle if needed.
-- A/B die position change, retangle PI frame die not cover all die. (Please refer illustration in mail)
-- ASECL add alignment key as last design.
-- ASECL may put dummy pattern in assigned area (refer illustration in mail), need to keep 500um clearance to passivation open.
-- Test die 1/2/3 not count as good die