In Figure 12, First, the master CRNGi, i = 1, 2 . . . , n, sequentially generates the information umi(k) required by each RNGi synchronization controller and in the slave RNGi, i = 1, 2 . . . , n, also sequentially generates the required information usi(k). umi(k) and usi(k) are, respectively, time-sharing selected by the selectors in the master and slave sides, then umi(k) and usi(k) is integrated to form the aforementioned controller (ui(k) = umi(k)+ usi(k)) and then the synchronization between master CRNGi and slave CRNGi, i = 1, 2 . . . , n can be guaranteed. Because the computing speed of the microcontroller is extremely fast, the large-scale master-slave CRNGs can also be synchronized quickly.