This is your standard planar MOSFET used in modern microprocessors (above 20nm; more advanced chips use a different kind of transistor)You have your source, drain and gate as the essential components. When voltage is applied to the gate, current flows from the source to the drain.When the gate is active, a channel forms between the source and drain, through the p substrate.In theory, on a perfect transistor, there should be no leakage, ie no current should flow when the gate is not active. The only power consumption is active/switching power when the gate is asserted.Here's where the problems start: over the years, engineers have been trying to reduce to size of these transistors. This is primarily done by reducing the distance between the source and drain, and thus the width of the gate, and it's surface area.The problem is that under a certain size, the gate has less and less control over the channel. A few electrons go through at first, but as you shrink the gate even further, you get a transistor that presents a HIGH output despite an inactive gate, and the whole transistor as a switch model falls apart, as you can no longer accurately control their behavior.For a long time, while not critical, this leaking would use up a significant share of the power budget in a microprocessor ( even modern chips have roughly half of their power being leakage). The chip designers would thus shut off parts of a chip that were not being used on the fly, or simply downclock those components.However, the leakage problem actually got worse to a point where the planar transistor no longer worked. That's why new transistor structures have been invented that increase the surface area of the gate, such as the current finfet transistor, or the the gate all around FET.