I. INTRODUCTION
The Consultative Committee for Space Data Systems
CCSDS) has produced over the years a de facto standard
Unified Turbo/LDPC Code
Decoder Architecture for
Deep-Space Communications
(
for all space-related communication systems. In the latest
versions of the standard [1] there has been an increment in
the foreseen downlink throughput for deep-space
communications, reaching up to tens of megabits per
second. Four channel coding schemes have been described
in [2] and consequently assembled into application-wise
forward-error-correction (FEC) schemes in [3]. Both turbo
[
4] and low-density-parity-check (LDPC) [5] codes are
currently contemplated for deep-space communications
[2]; while the suggested turbo codes target stricter bit error
rate (BER) constraints, LDPC codes have been recently
included in the standard and have higher rate, and they are
currently subject to CCSDS experimentation [6]. Both
turbo and LDPC codes are common in on-Earth wireless
communication systems; however, throughput
requirements are much higher than those for deep-space
communications, while frame error rate (FER) constraints
are more relaxed. In fact, spacecraft-to-Earth
communications are characterized by limited amounts of
available power and long transmission times, and a failed
reception and consequent retransmission are often
unacceptable. Thus, ad hoc powerful FEC schemes must
be devised.
A FEC relying on the serial concatenation of turbo and
LDPC codes has been proposed in [7]; thanks to its very
good error correction capabilities, it has been deemed
suitable for the extremely critical deep-space
CARLO CONDO
GUIDO MASERA, Senior Member, IEEE
Politecnico di Torino
Italy
Deep-space communications are characterized by extremely
critical conditions; current standards foresee the usage of both turbo
and low-density-parity-check (LDPC) codes to ensure recovery from
received errors, but each of them displays consistent drawbacks.
Code concatenation is widely used in all kinds of communication to
boost the error correction capabilities of single codes; serial
concatenation of turbo and LDPC codes has been recently proven
effective enough for deep space communications, being able to
overcome the shortcomings of both code types. This work extends
the performance analysis of this scheme and proposes a novel
hardware decoder architecture for concatenated turbo and LDPC
codes based on the same decoding algorithm. This choice leads to a
high degree of datapath and memory sharing; postlayout
implementation results obtained with complementary metal-oxide
semiconductor (CMOS) 90 nm technology show small area
occupation (0.98 mm2) and very low power consumption (2.1 mW).
communications. To the best of our knowledge, no
implementation solution for the concatenated scheme has
been proposed so far, but decoders for both turbo and
LDPC codes are present in the state of the art, mainly
targeting wireless communications. Multicode and
multistandard decoders that make flexibility their primary
concern have also been introduced recently [8–13]; they
are characterized by different degrees of datapath and
memory sharing.
This work proposes a decoder for concatenated turbo
and LDPC codes targeting deep-space communications.
The usage of the same decoding algorithm for both codes
greatly reduces the area overhead of the concatenated
scheme decoder with respect to a single LDPC or turbo
code decoder. In fact, it allows one to exploit a high degree
of datapath sharing and obtain very low power consumption
and area occupation. In addition to deep-space
communications, the proposed solution could be also
useful in further applications where retransmission of lost
packets is not allowed, such as, for example, broadcasting.
The rest of the paper is organized as follows: Section II
introduces turbo and LDPC code decoding, while
Section III describes the concatenated FEC schemes and
Manuscript received June 13, 2013; revised December 6, 2013,
March 11, 2014; released for publication June 26, 2014.
DOI. No. 10.1109/TAES.2014.130384.
Refereeing of this contribution was handled by M. Rice.
Authors’ address: Politecnico di Torino, Electronics and
Telecommunications, Corso Duca degli Abruzzi, 24, Torino, 10129 Italy, their performance. The hardware structure of the proposed
E-mail: (carlo.condo@polito.it).
decoder is explained in Section IV, and Section V gives
the results of the implementation. Finally, conclusions are
0
018-9251/14/$26.00 C 2014 IEEE
drawn in Section VI.
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 50, NO. 4 OCTOBER 2014
3115
II. TURBO AND LDPC DECODING
codeword must satisfy, i.e. H ·x = 0, where x is the
codeword of length N. Various decoding approaches are
possible, depending on the graph representation of H, but
the most performing one is the layered decoding approach
Turbo codes can be obtained by concatenating in
parallel two convolutional code encoders. The dual
encoding structure is reflected on the decoder th