I. INTRODUCTIONThe Consultative Com

I. INTRODUCTION
The Consultative Committee for Space Data Systems
CCSDS) has produced over the years a de facto standard
Unified Turbo/LDPC Code
Decoder Architecture for
Deep-Space Communications
(
for all space-related communication systems. In the latest
versions of the standard [1] there has been an increment in
the foreseen downlink throughput for deep-space
communications, reaching up to tens of megabits per
second. Four channel coding schemes have been described
in [2] and consequently assembled into application-wise
forward-error-correction (FEC) schemes in [3]. Both turbo
[
4] and low-density-parity-check (LDPC) [5] codes are
currently contemplated for deep-space communications
[2]; while the suggested turbo codes target stricter bit error
rate (BER) constraints, LDPC codes have been recently
included in the standard and have higher rate, and they are
currently subject to CCSDS experimentation [6]. Both
turbo and LDPC codes are common in on-Earth wireless
communication systems; however, throughput
requirements are much higher than those for deep-space
communications, while frame error rate (FER) constraints
are more relaxed. In fact, spacecraft-to-Earth
communications are characterized by limited amounts of
available power and long transmission times, and a failed
reception and consequent retransmission are often
unacceptable. Thus, ad hoc powerful FEC schemes must
be devised.
A FEC relying on the serial concatenation of turbo and
LDPC codes has been proposed in [7]; thanks to its very
good error correction capabilities, it has been deemed
suitable for the extremely critical deep-space
CARLO CONDO
GUIDO MASERA, Senior Member, IEEE
Politecnico di Torino
Italy
Deep-space communications are characterized by extremely
critical conditions; current standards foresee the usage of both turbo
and low-density-parity-check (LDPC) codes to ensure recovery from
received errors, but each of them displays consistent drawbacks.
Code concatenation is widely used in all kinds of communication to
boost the error correction capabilities of single codes; serial
concatenation of turbo and LDPC codes has been recently proven
effective enough for deep space communications, being able to
overcome the shortcomings of both code types. This work extends
the performance analysis of this scheme and proposes a novel
hardware decoder architecture for concatenated turbo and LDPC
codes based on the same decoding algorithm. This choice leads to a
high degree of datapath and memory sharing; postlayout
implementation results obtained with complementary metal-oxide
semiconductor (CMOS) 90 nm technology show small area
occupation (0.98 mm2) and very low power consumption (2.1 mW).
communications. To the best of our knowledge, no
implementation solution for the concatenated scheme has
been proposed so far, but decoders for both turbo and
LDPC codes are present in the state of the art, mainly
targeting wireless communications. Multicode and
multistandard decoders that make flexibility their primary
concern have also been introduced recently [8–13]; they
are characterized by different degrees of datapath and
memory sharing.
This work proposes a decoder for concatenated turbo
and LDPC codes targeting deep-space communications.
The usage of the same decoding algorithm for both codes
greatly reduces the area overhead of the concatenated
scheme decoder with respect to a single LDPC or turbo
code decoder. In fact, it allows one to exploit a high degree
of datapath sharing and obtain very low power consumption
and area occupation. In addition to deep-space
communications, the proposed solution could be also
useful in further applications where retransmission of lost
packets is not allowed, such as, for example, broadcasting.
The rest of the paper is organized as follows: Section II
introduces turbo and LDPC code decoding, while
Section III describes the concatenated FEC schemes and
Manuscript received June 13, 2013; revised December 6, 2013,
March 11, 2014; released for publication June 26, 2014.
DOI. No. 10.1109/TAES.2014.130384.
Refereeing of this contribution was handled by M. Rice.
Authors’ address: Politecnico di Torino, Electronics and
Telecommunications, Corso Duca degli Abruzzi, 24, Torino, 10129 Italy, their performance. The hardware structure of the proposed
E-mail: ([e-mail]).
decoder is explained in Section IV, and Section V gives
the results of the implementation. Finally, conclusions are
0
018-9251/14/$26.00 C 2014 IEEE
drawn in Section VI.
IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 50, NO. 4 OCTOBER 2014
3115



II. TURBO AND LDPC DECODING
codeword must satisfy, i.e. H ·x = 0, where x is the
codeword of length N. Various decoding approaches are
possible, depending on the graph representation of H, but
the most performing one is the layered decoding approach
Turbo codes can be obtained by concatenating in
parallel two convolutional code encoders. The dual
encoding structure is reflected on the decoder th

結果 (中文) 3:

一、引言空间数据系统咨询委员会CCSDS）多年来一直在制作阿德的事实上的标准大学fiED涡轮/ LDPC码解码器架构深空通信（所有的空间相关的通信系统。在最新的标准的[ 1 ]有一个增量版本可以预见的下行链路吞吐量的深空通信，达到几十兆比特每二。四信道编码方案进行了描述在[ 2 ]，因此组装成应用智慧前向纠错（FEC）在[ 3计划]。涡轮【4 ]和低密度奇偶校验（LDPC）[ 5 ]码目前设想用于深空通信[ 2 ]；而提出的Turbo码的目标更严格的误码率（BER）的限制，LDPC码已被最近纳入标准，具有更高的速度，和他们目前受CCSDS实验[ 6 ]。两Turbo码和LDPC码是常见的在地球无线通信系统；然而，吞吐量要求比深空高多了通信，而帧错误率（FER）约束更轻松。事实上，宇宙飞船到地球通信的特点是数量有限的可用功率和较长的传输时间，一个失败的接待和随之而来的转播往往不可接受的。因此，Ad Hoc网络强大的FEC方案必须设计。一个FEC依托Turbo码的串行级联和LDPC码已在[ 7 ]提出的；由于其非常好的纠错能力，它已被视为适用于极为关键的深空卡罗公寓GUIDO MASERA，高级会员，IEEE意大利都灵理工大学意大利深空通信的特点是非常临界条件；现行标准预见turbo的使用低密度奇偶校验码（LDPC）确保恢复接收到的错误，但他们每个人都显示一致的弊端。级联码被广泛应用于各种通信提高单码的纠错能力；串行Turbo码和LDPC码级联最近已被证明有足够的深空通信，能够克服缺点的代码类型。这项工作的延伸该方案的性能分析，提出了一种新的对于级联Turbo和LDPC解码器的硬件架构基于相同的译码算法代码。这种选择导致一个数据通路和内存共享程度高；后布局与互补金属氧化物得到的执行结果半导体（CMOS）90纳米技术显示面积小职业（0.98平方毫米）和非常低的功率消耗（2.1兆瓦）。通信。尽我们所知，没有实施方案为级联方案被提出至今，但两个涡轮增压器和解码器LDPC码是在艺术的状态存在，主要瞄准无线通信。Multicode和多标准解码器的灵活性使fl原关注还介绍了最近8–[ 13 ]；他们具有不同程度的数据通路和内存共享。本文提出了一种级联的Turbo解码器针对深空通信和LDPC码。相同的译码算法代码的使用大大降低了级联的面积开销相对于一个LDPC或Turbo解码器编码解码器。事实上，它可以利用高度对数据共享和获取极低的功耗面积占用。除了深空通信，提出的解决方案也可以在进一步的应用中，重传丢失的有用包是不允许的，例如，例如，广播。本文的其余部分安排如下：第二节介绍了Turbo码和LDPC码的译码，而第三节介绍了级联FEC方案手稿收到2013年6月13日；2013年12月6日修订，2014年3月11日2014年6月26日出版；公布。DOI。10.1109/taes.2014.130384号。裁判这个贡献是由M. Rice。作者地址：意大利都灵理工大学，电子Corso Duca degli Abruzzi，电信，24，Torino，10129意大利，他们的表现。提出的硬件结构电子邮件：（Carlo。公寓@波利托，）。解码器是在第四节和第五节给出解释，实施的结果。最后，结论是零018-9251 / 14 / 26美元C 2014 IEEE画在第六IEEE航空航天与电子系统50卷，4号十月2014三千一百一十五II。Turbo码和LDPC码的译码码字必须满足，即H·x = 0，其中x是长度的码字是各种解码方法可能，这取决于H的图表示，但最不良的是分层译码方法Turbo码可以将获得的平行的两个卷积码编码器。双编码结构重新fl连接在德