The efficiency degradation at low drain voltage for a class-E power amplifier designed with a MOSFET transistor has been analyzed by taking nonlinear transistor output capacitance into consideration. Theoretical analysis and numerical results have shown that the ZVS condition of a class-E amplifier, designed at a nominal drain dc supply voltage, is no longer satisfied in a polar transmitter in which the drain dc supply voltage is variable due to the amplitude modulation and the power control.
The degraded drain efficiency is mainly caused by the energy dissipated on during the OFF–ON transition instant. Furthermore, the efficiency enhancement method, found in the analysis and numerical results of the effects of duty ratio variations,are proposed by adjusting the gate dc bias voltage. The validity of the analysis and feasibility of the efficiency enhancement method are verified by an experimental LDMOS class-E power amplifier designed at 100 MHz. This amplifier manifests efficiency degradation at the low drain voltage ( 6 V); approximately 7.5% drain efficiency improvements and a 9.26-dB dynamic range extension are obtained with the gate dc bias adjustments method.