Right-Justified ModeRight-justified

Right-Justified Mode
Right-justified timing uses the WS clock to define whether the data is being transmitted for the left channel
or right channel. The WS is high for the left channel, and low for the right channel (requires the WS polarity
control bit to be set to 1). A bit clock running at a minimum of 2 x sample width x sample frequency is used
to clock the data. Data is captured in a 24-bit shift register until the WS toggles. When the WS toggles the
last 24 bits, 16 bits or 8 bits are transferred to the channel indicated by the previous state of WS. In rightjustified mode, the LSB of data is always clocked by the last bit clock before the WS transitions. The data
is written MSB first and is valid on the rising edge of bit clock. All leading bits are ignored.

結果 (中文) 1:

右对齐模式右对齐的时机使用 WS 时钟来定义是否正在为左声道传输数据或右声道。WS 是为左声道，高和低 （要求 WS 极性的右声道控制位设置为 1）。使用运行 2 x 采样频率的试样宽度至少位时钟到时钟数据。在一个 24 位的移位寄存器中捕获数据，直到 WS 切换。当 WS 切换最后的 24 位，16 位或 8 位转移到通道由 WS 的以前的状态。在 rightjustified 模式下，数据 LSB 总是由 WS 过渡前的最后一位时钟时钟频率。数据第一次写 MSB 和对位时钟的上升沿有效。所有前导位将被忽略。